TM
11-6625-3041-30/TO
33A1-8-908-12
1-13. TRANSMIT 1 (A3) NRZ OUT (CONT)
Al 1 transmit circuits associated with the three different timing
TIMING
-
sources are controlled by the front panel TIMING control. The
Control
output from this control is a 2-bit binary code that determines
the-timing source as follows:
TIMING Control
Output Code
Setting
A
B
LOOPED
0
1
T r a n s m i t timing is derived from signals
applied to receiver input (refer to
Transmit timing is derived from external
STA
CLK
1
0
STA CLK
Input
signal applied-to the front panel STA CLK
input connector. In this timing mode, a
front panel indicator lights when a signal
is applied to the connector.
MASTER
1
1
Transmit timing is derived from the Master
Osc.
All three timing signals (Sta Clk, Looped, and Master) are
Timing Sel
applied to the Timing Sel. Depending on the setting of the
TIMING control, one of the inputs is selected as the output.
The output from the Timing Sel is applied to an amplifier,
BALANCED
TMG OUT
converted to a balanced (2-wire) output, and applied to the
front panel BALANCED TMG OUT connector. The l-level 06 output
from Decode I enables this amplifier only for the 126-4608
family of DATA RATES (balanced NRZ).
The output from the Timing Sel is also applied to the input of
Fam Sel
the Fam Sel. A 0-level 05 output from Decode I (576 family of
DATA RATES) selects this input as the output from the Fam Sel.