TM 11-6625-3041-30/TO 33A1-8-908-12
1-13. TRANSMIT 1 (A3) NRZ OUT (CONT)
The output of the PR Gen is applied to the input of the Single
Single
Error Inject. A second input is from a latch activated by the
Error
front panel SINGLE ERROR pushbutton. Each time the button is
Inject
pressed, it injects an error (a 0 where a 1 would be or a 1
where a O would be).
The
output of the Single Error Inject is applied to the Unbal
Unbal/Bal
Bal Data Retime circuits. Both operate in the same manner
Data Retime
and
and
are used to ensure the timing outputs and data outputs
are
synchronized.
The Unbal Data Retime is enabled when both the 05 and 06 out-
UNBALANCED
DATA OUT
puts of Decode I are O (576 family DATA RATE). Its output
is applied to an amplifier and through a filter to the front
panel UNBALANCED DATA OUT connector.
The Bal Data Retime is enabled when the 06 output of Decode I
BALANCED
DATA OUT
is 1 (128-4608 family DATA RATE). Its output is applied to an
amplifier, converted to a balanced (2-wire) output, and applied
to the front panel BALANCED DATA OUT connector.
1-14. TRANSMIT 1 AND 2 (A3&A4) DIPHASE OUT
Diphase
Two outputs from the NRZ Clock Gen are applied to the Diphase
Clock Gen
Clock Gen input. One is 614.4 kHz derived from the 9.216 MHz
Master Osc output. The other is 512 kHz derived from the
8.192 Master Osc output.
The Diphase Clock Gen has seven different divider outputs.
These outputs produce the seven rates associated with diphase
outputs. Each rate is twice the actual diphase DATA RATE set-
ting because two transitions are required for each logic O
bit, one a half-bit later than the other.