TM 11-6625-3041-30/TO 33A1-8-908-12
1-15. RECEIVE 1 (A5) NRZ IN
The unbalanced data signal is applied to the front panel
UNBAL
DATA IN
UNBALANCED DATA IN connector, through a filter, and to an
amplifier. A l-level 05 output from Decode II enables the
amplifier only for the 576 (ATACS) family DATA RATE (unbalanced
NRZ) .
Unbal
The output from the amplifier is applied to the input of the
Data Delay
Unbal Data Delay. The Unbal Data Delay delays the data in-
put sufficiently to ensure it lags the timing input.
The unbalanced timing signal is
applied to the front panel
UNBAL
UNBAL TMG IN connector, through
a filter, and to an amplifier.
TMG IN
A 1-level 05 output from Decode
11 enables the amplifier only
for the 576 (ATACS) family DATA
RATE (unbalanced NRZ).
The output of the
Unbal
Unbal Data Delay is
Data Retime
applied to the D
input of the Unbal
Data Retime, a D
flip-flop.
The clock input to
the flip-flop is the
unbalanced timing
signal . It is used to clock the data out of the flip-flop to
ensure the data input is in phase with the timing input.
BAL
The balanced data signal is applied to the front panel BALANCED
DATA IN connector and to an amplifier. A O-level 04 and a
DATA IN
O-level 05 output from Decode II enable the amplifier only
for the 128-4608 family DATA RATES (balanced NRZ).