TM 11-6625-3025-14/ET426-AA-MMA-010/E154 VII210/T.O. 33A1-8-902-1-1
Section II. DETAILED CIRCUIT DESCRIPTION
4-4.
Sync Generation. The master oscillator circuitry develops a pulse train from a stable crystal-controlled oscillator
circuit whose risetimes act as the timing reference for generation of all waveforms. The crystal-controlled master oscillator
is located on the drive/blanking card (figure FO-3), operating at 200 times the horizontal rate. The 200H pulses are
counted to 20H by a decade integrated circuit counter, then the 20H pulses are counted down to 2H by counter Z3.
EIA Standard RS-343 requires that serrations of horizontal rate be produced during the sync interval. Serration
polarity is opposite that of the horizontal pulses to permit detection of the vertical sync. Therefore, the negative trailing
edge of the serration pulses becomes a sync timing reference as opposed to the negative leading edge of the horizontal
sync pulses. The 2H pulses from the master oscillator are routed to a monostable multivibrator where a delay is produced
to generate the serration pulse width. From this point on, the trailing edge of the serration pulse is used as the sync timing
reference. However, the leading edge of blanking must take place previous to the timing reference. Therefore, a second
monostable multivibrator develops a time delay to generate the proper start of blanking. This control establishes the width
of horizontal front porch (time from start of blanking to start of sync).
The 2H pulses are routed to the serration monostable (Z9) and front porch monostable (Z10) on the sync card
(figure FO-4). The front porch pulse trailing edge becomes the timing reference for horizontal and vertical blanking.
Integrated circuit counter Z5B on the sync count card (2:1 count) (figure FO-5), develops the H rate timing reference
applied to the H drive monostable (Z7) and to the H blanking monostable (Z8) on the drive/blanking card.
Development of an interlaced synchronizing waveform requires that the vertical information be counted from the
horizontal. Therefore, the reference timing edge for blanking is routed to the sync count card for this operation.
The sync count card (figure FO-5) contains a series of integrated circuit J-K flip-flops to count the proper number
of horizontal lines which will be developed in each vertical field. A different count is required for each scanning rate. This
is accomplished by utilizing a group reset technique. Outputs from the counter stages Z5 through Z10 (except Z5B) are
applied to a control gate that is connected to a common buss (Z2). A mixture of different counted pulses is then acquired
which develops a reset pulse after an appropriate interval, according to programming jumpers that determine which counts
are applied to the gate. A matrix is provided on the card for selection of the reset counts as desired for any one scan rate.
The reset pulse is developed by monostable Z1 and routed to the J-K flip-flops where all elements in the counter are reset
simultaneously. The trigger resulting from this reset is then used for initiation of vertical pulses.
4-8
