TM 11-6625-3025-14/ET426-AA-MMA-010/El54 VII210/T.O. 33A1-8-902-1-1
ground potential. The signal from common collectors Q19 and Q20 is routed to range limiting resistor R47 and blanking
level control R46. The signal is then fed to emitter-follower Q18 which drives the current mixing network through R34. The
sync signal is processed by Q3 and Q4 with the level controlled by R11 and fed into the network by R8 to Q6. All three
components of the composite signal are formed at R35. Circuit dc levels have been chosen to generate the blanking level
(blacker-than-black) at near ground potential.
The signal is routed to emitter-follower Q14, which filters the signal slightly to remove spikes from the very fast rise
and fall times (C5) and bias the signal negative to compensate for dc shifts encountered in the output driver. The push-
pull complimentary pair driver (Q16 and Q17) is fed by emitter-follower Q15, which also includes diodes CR1 and CR2 to
compensate for base-to-emitter voltage drops in the driver transistors. Source impedance is determined by the built-out
resistor network R42, R44 and R61.
4-6.
Video Processing. Many functions are to be developed in either a white or black pattern format (bar, dot,
window, H stripe, V stripe, etc.). The circuitry on the polarity card (figure FO-9) performs this function as well as
developing the flat field function. Digital signals from various function circuits are developed at R29 (pin Y). They are fed to
emitter-follower Q10 which is biased negatively through R27 and R28. When white level is developed, the emitter of Q10
is high, thus back-biasing diode CR7. When Black level is developed the emitter of Q10 goes low, allowing CR7 to
conduct. Transistor Q3 is then turned "off", causing a high level to be developed at the collector of Q3, and a low level at
the collector of Q2. Therefore, both polarities of signal are available; inverted at Q3 and non-inverted at Q2. Selection is
made through stages Q1 and Q4 which have a common collector load (R15). If voltage is applied to R10 through pin C,
the signal is passed through CR2, and Q4 is turned on causing a non-inverted (white) signal to be developed at R15, with
Q1 biased off. If voltage is applied to pin L, diode CR1 and Q1 are operational, causing an inverted (black) signal to be
developed at R15; Q4 is biased off.
In some cases the digital signal at R15 is locked at white level (as for the flat field and gray scale functions). This
is insured by control stages Q8 and Q9. voltage is applied at input pin J through isolating diode CR5 and causes Q8 to
saturate, forcing voltage at R1 and R10 low, and therefore, locking both Q1 and Q4 "off". Therefore, the signal at R15 will
remain at a high (white) level. Signal information which does not need polarity processing can be inserted at pin P to load
resistor R15, such as the reference signal in the resolution function. The signal at R15 is blanked by stage Q5 to ensure
video black level through the horizontal and vertical retrace intervals. The signal is inverted by Q6 and fed to emitter-
follower Q7 and is routed to the video emitter coupled input.
4-12
