TM 11-6625-3025-14/ET426-AA-MMA-010/E154 VII210/T.O. 33A1-8-902-1-1
the vertical interval, as determined by gate Z8B. Equalizing pulses at 2H rate are introduced from the first to third and sixth
to ninth lines through gate Z8C which is controlled by inverter Z6D, using the control pulse from gate Z3B. Serrations at
2H rate produced by monostable Z9, are inserted from the third to sixth lines of the vertical interval by gate Z7A.
b. Without Equalizing Pulses and Serrations. Equalizing pulses are not permitted through gate Z8C, which is
turned off by inverter Z6C, in turn controlled by grounding the inverter input at resistor R12 (pin M). This also turns off gate
Z8B and turns on Z7C, deleting sync pulses from the third to sixth lines of the vertical interval, substituting H-rate sync
pulses for the 2H equalizing pulses.
Serrations are blocked from passing through gate Z7A by the control level at R9, as controlled by inverter Z6F and
the voltage at R8 (pin T). A vertical sync pulse without H or 2H information results.
c. Military Waveform. The sync waveform used in certain systems requires that there be no H rate of 2H content
in the vertical front porch and that there be no equalizing pulses and serrations as well as no horizontal front porch. Pins
M, T and U are grounded as in (b). The sync pulse is developed by Z4, triggered by the output of gate Z8A. This gate
combines the serration and front porch pulses so that Z4 will be triggered by the longer of the two pulses usually
serrations. However, gate ZID blocks the serration pulses, causing Z4 to be triggered by the trailing edge of the front
porch pulse, coincident with the start of blanking and drives. Gate Z7D normally would be blocked by low voltage at pin N.
When it is not blocked (+5v at pin N), gate Z7D deletes the sync pulses during the vertical front porch as commanded by
the output of bistable Z2A and Z2B.
Sync generator outputs (H drive, V drive, blanking and sync) are processed through the pulse output card (figure
FO-6) to properly drive coaxial cable at the required amplitude and impedance. Four identical circuits are used. For
instance, the H drive pulse input is routed from pin B through bias network R1 and R2 to Q1. The collector waveform from
Q1 is routed to push-pull output drivers, Q2 and Q3. Diodes CR1 and CR2 compensate for the base-to-emitter drop of the
output drivers. Series resistors R4 and R5 provide the proper cable drive source impedance, and R6 provides a ground
return path. The output is ac coupled through C1 to the output (pin W). Pulse amplitude control is obtained by the voltage
level applied to collector load R3 established by series regulator Q13, and controlled by potentiometer R25.
4-5.
Basic Video Signal Development. The incoming H drive, V drive, blanking and sync signals are routed to the
pulse input card (figure FO-7) where the pulses are processed to uniform level and risetime. The outputs from this card
are separated into vertical and horizontal components which control all subsequent operations in signal development. The
card contains four identical circuit sections.
4-10
