TM
11-6625-3041-30/TO
33A1-8-908-12
1-16. RECEIVE 1 (A5) DIPHASE IN (CONT)
The data output of
Binary
the Diphase to
Retime
Binary Conv is ap-
plied to the D
input of the Binary
Retime, a D flip-
flop.
The clock input to
the flip-flop is the
clock output from the Diphase Rate Sel, divided by 2 so that
it is at the same rate as the DATA RATE control setting.
The clock input is used to clock the data out of the flip-flop
to ensure the data input is in phase with the timing input.
The output from the Binary Retime is applied to the input of
Data
the Data Fam Sel. Two other inputs are from the Unbal and
Fam Sel
Bal Data Retime.
One of the inputs is selected as the output, depending on the
setting of the DATA RATE control (through the 04 and 05 outputs
from Decode II). For example, a Decode 11 output of 10 selects
the .6-32 family (diphase) as the output.
The clock output from the Diphase Rate Sel, divided by 2, is
NRZ/Diphase
applied to the NRZ/Diphase Clock Sel. A second input is the
Clock Sel
NRZ clock signal from the Clock Fam Sel.
One of the inputs is selected as the output, depending on the
setting of the DATA RATE control (through the 04 output from
Decode 11). For example, a Decode II output of 1 selects
the .6-32 family (diphase) as the output.
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