TM 11-6625-3041-30/TO 33A1-8-908-12
1-17. RECEIVE 1 (A5) ERROR DETECTION (CONT)
Each real error in the input data produces three error pulses
True Error
in the Error Det output because there are three paths from the
Count
data input to the error output.
To prevent an error count of three times the actual input errors,
the output of the Error Det is applied to the input of the True
Error Count. The True Error Count is a divide-by-3 counter that
produces one output pulse for every three it receives.
The output of the True Error Count is applied to the input of
Error
the Error Shape.
Shape
The true errors output from the Error Shape is applied to the
ERRORS counter and BER indicator circuits on the Receive 2
card.
Before the PR Gen is synchronized to the input data, the Error
Sync Error
Det will produce a number of error pulses up to one less than
Inhibit
14 in the SG-1139).
To prevent an error count during the synchronization process, a
Sync Error Inhibit is used. The Sync Error Inhibit is a divide-
by-16 counter that is driven by the clock output from the NRZ/
Diphase Clock Sel. It is set to zero (initialized) by a signal
from the Receive 2 card (refer to para 1-19, BER control) which
occurs when power is first applied, when timing inputs are first
applied, or when the RESET button is pushed, etc.
During the time the first 16 clock pulses are applied, after
initialization, the output from the Sync Error Inhibit prevents
operation of the True Error Count and Error Shape so that sync
errors are not counted.
1-17