TM 11-6625-3025-14/ET426-AA-MMA-010/E154 VII210/T.O. 33A1-8-902-1-1
Basically the resolution pattern is the alternate black and white video developed by the output of an astable multivibrator.
One resolution card is produced for each burst rate with selected components to produce the desired repetition rate.
Additional control circuitry is included on these cards to control generation of the exact signal format desired. The
multiburst and multiburst clock cards develop the control functions which are distributed to these control components, and
the multiburst card performs other auxiliary functions, including development of the video level produced between bursts.
The multiburst card contains a clock multivibrator Q2 and Q7 which is synchronized to the horizontal blanking by
clamp circuit Q1 and CR1. Pulses from this controlled astable control the width of resolution signal bursts and the space
between bursts. Repetition rate is adjustable by divider R1 and R11 which controls constant current transistors Q4 and Q5
to permit multiburst development within the active scan line time for the particular scan rate in use. This duty cycle is
directed for the various resolution cards by emitter-follower Q12 after processing through Q8, Q9 and Q11 to insert
blanking. If separated resolution bursts are to be developed, the astable operates in normal fashion, being clamped to the
input H-rate control at CR2 during the H blanking interval. For generation of a continuous pattern, voltage is removed from
the clock processing Q8. Therefore, only the blanking waveform is developed at the collector of Q10.
The reference function is a black/white pulse output at the clock rate. Selection of the reference function applies
voltage to collector load resistor R33 through isolating diode CR4, causing a signal to be developed at output stage Q13.
All resolution cards are identical except for component values (C5, C3, R3, R4, R10 and R22) which are selected
to provide the desired repetition rate. Signals are developed by astable multivibrator Q13 and Q21 and are routed to
isolation emitter-follower Q22 to the signal buss. Resolution signals are routed to the emitter-coupled input of the video
card. The astable is controlled by clamp diode CR3 and emitter-follower 010. Whenever Q10 develops a signal below
ground level, CR3 conducts and the base of Q13 is locked in the "off" state, forcing the astable to remain inoperative.
When Q10 develops a higher level of voltage, CR3 is non-conducting, effectively isolating the control stage and permitting
the astable to operate normally.
Control signal for the astable Q13 and Q21 is processed by Q11 and Q12. The duty cycle of signal development
is established by the signal from the multiburst circuits as directed through R32 to Q12. In turn, load resistor R26 controls
the output level of emitter-follower Q10 through bias network R27 and R29. When Q12 turns on due to a "high" condition
of the input duty cycle signal, a low level is developed at the emitter of Q10, clamping the astable. When Q12 is biased
"off", the astable is operative.
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