TM 11-6625-3025-14/ET426-AA-MMA-010/E154 VII210/T.O. 33A1-8-902-1-1
Development of the multiburst signal requires that each resolution card operate in proper sequence. An integrated
circuit ring counter on the multiburst clock card is used for control to develop the multiburst signal sequence. Additional
control is provided to load resistor R26 through Q11. Transistor Q11 clamps the astable inoperative. At the proper time,
Q11 is turned "off" and control stage Q10 then permits the astable to develop a burst.
The basic clock signals for the multiburst ring counter is developed on the multiburst card. Clock and reset signals
are developed by Z1C and Z1D. The ring counter is reset at the end of every tv line to assure a proper start for each
horizontal line regardless of the circuit condition at the end of the previous line. Flip-flop Z2B develops an initial prime
pulse to command the first stage of the ring counter Z2 to operate. The X3B stage controls development of the white-
black reference bar at the start of the multiburst array.
The multiburst clock card contains logic to terminate the sequential multiburst operation after the occurrence of the
last burst sequence. Integrated circuit Z8A (J-K flip-flop) is the last stage of the ring counter which controls resolution card
operation. When this stage operates, flip-flops Z9A and Z9B change state, causing Q14 on the multiburst card to turn on,
developing a low state at the emitter of Q1 and stopping clock operations at the end of the multiburst sequence. The ring
counter reset (occurring during the blanking interval) returns Z9A to the "off" state. Transistor Q15 provides normal
blanking control to the multiburst card.
The multiburst card also contains auxiliary circuits to operate the resolution cards. Transistor Q12 generates the
level of gray which will be presented between bursts. Transistor Q18 develops a black level between bursts when
minimum APL is selected. These are controlled by transistors Q20, Q21, Q22 and Q23 as dictated by inputs from the
clock to properly phase the video (Q22), the ring counter (Q20) to prohibit development of a gray level after the multiburst
is complete, (Q23) to prohibit operation during the continuous mode.
Provision is made to switch a reference segment into the multiburst mode. Voltage is applied to counters Z1, Z2
and Z3 of the multiburst clock card to locate the reference segment. The positive pulse is routed to Q11 on the multiburst
card to inhibit resolution pattern development. The negative pulse is routed to Q17 to permit development of the reference
information by Q13 at the proper time; voltage is applied to R33 also.
4-10. H Stripe, V Stripe, and Window. The window pattern is developed with reference to the top and the left edge of
the television raster. Basically, generation is accomplished by two H and two V monostable multivibrators. The first one
times the spacing from the top (or left edge) of the point at which pattern is developed, and the second establishes the
time through which the pattern will be generated. The appropriate circuits, including mixers, are placed on the H window
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